1. Field of the Invention
This invention relates to a technique for driving a plasma display panel, and more particularly to a plasma display panel driving method and apparatus employing an asymmetry sustaining that is adaptive for a high-speed driving.
2. Description of the Related Art
Recently, a plasma display panel (PDP) feasible to a manufacturing of a large-size panel has been highlighted as a flat panel display device. The PDP typically includes a three-electrode, alternating current (AC) surface discharge PDP that has three electrodes and is driven with an AC voltage as shown in FIG. 1.
Referring to FIG. 1, a discharge cell of the three-electrode, AC surface discharge PDP includes a scanning/sustaining electrode 12Y and a common sustaining electrode 12Z formed on an upper substrate 10, and an address electrode 20X formed on a lower substrate 18. On the upper substrate 10 in which the scanning/sustaining electrode 12Y is formed in parallel to the common sustaining electrode 12Z, an upper dielectric layer 14 and a protective film 16 are disposed. Wall charges generated upon plasma discharge are accumulated in the upper dielectric layer 14. The protective film 16 prevents a damage of the upper dielectric layer 14 caused by the sputtering generated during the plasma discharge and improves the emission efficiency of secondary electrons. This protective film 16 is usually made from MgO.
A lower dielectric layer 22 and barrier ribs 24 are formed on the lower substrate 18 provided with the address electrode 20X, and a fluorescent material 26 is coated on the surfaces of the lower dielectric layer 22 and the barrier ribs 24. The address electrode 20X is formed in a direction crossing the scanning/sustaining electrode 12Y and the common sustaining electrode 12Z. The barrier ribs 24 are formed in parallel to the address electrode 20X to prevent an ultraviolet ray and a visible light generated by the discharge from being leaked to the adjacent discharge cells. The fluorescent material 26 is excited by an ultraviolet ray generated upon plasma discharge to produce a red, green or blue color visible light ray. An inactive gas for a gas discharge is injected into a discharge space defined between the upper/lower substrate and the barrier rib.
Referring to FIG. 2, a PDP 30 adopting a block division system is divided into an upper block 38 and a lower block 40 for a driving. A discharge cell 1 is provided at each intersection among scanning/sustaining electrode lines Y1 to Ym, common sustaining electrode lines Z1 to Zm and address electrode lines X11 to X1n and X21 to X2n. The address electrode lines X11 to X1n and X21 to X2n are opened at a boundary line between the upper block 38 and the lower block 40.
A driving apparatus for driving such a PDP 30 includes a first scanning/sustaining driver 32A connected to the scanning/sustaining electrode lines Y1 to Ym/2 in the upper block 38, a second scanning/sustaining driver 32B connected to the scanning/sustaining electrode lines Ym/2+1 to Ym in the lower block 40, a common sustaining driver 34 connected to the common sustaining electrode lines Z1 to Zm, a first address driver 36A connected to the address electrode lines X11 to X1n in the upper block 38, a second address driver 36B connected to the address electrode lines X21 to X2n in the lower block 40, and a controller for controlling the first and second drivers 36A and 36B.
The controller 39 applies control signals XE/Rup, Xsusup, XE/Rdn and Xsusdn for energy recovery circuits included in the first and second address drivers 36A and 36B to the first and second address drivers 36A and 36B. The first scanning/sustaining driver 32A applies a scanning pulse and a sustaining pulse to the scanning/sustaining electrode lines Y1 to Ym/2 in the upper block 38. The second scanning/sustaining driver 32B applies a scanning pulse and a sustaining pulse to the scanning/sustaining electrode lines Ym/2+1 to Ym in the lower block 40.
The first address driver 36A applies a data pulse synchronized with the scanning pulse to the address electrode lines X1 to X1n in the upper block 38. The second address driver 36B applies a data pulse synchronized with the scanning pulse to the address electrode lines X21 to X2n in the lower block 40. The common sustaining driver 34 applies a sustaining pulse to all the common sustaining electrode lines Z1 to Zm included in the upper/lower blocks 38 and 40 simultaneously.
Such a PDP 30 divides one frame into a plurality of sub-fields having a different discharge frequency for a driving so as to express a gray level of a picture. Each sub-field is again divided into a reset interval for uniformly causing a discharge, an address interval for selecting the discharge cell and a sustaining interval for expressing the gray level depending on the discharge frequency. For instance, when it is intended to display a picture of 256 gray levels, a frame interval equal to 1/60 second (i.e. 16.67 msec) is divided into 8 sub-fields. Each of the 8 sub-fields is again divided into a reset interval, an address interval and a sustaining interval. The reset interval and the address interval of each sub-field are equal, whereas the sustaining interval is increased at a ration of 2n (wherein n=0, 1, 2, 3, 4, 5, 6 and 7). Since the sustaining interval becomes different at each sub-field as mentioned above, the gray levels of a picture can be expressed.
A driving of such a PDP 30 requires a high voltage more than hundreds of volts. Accordingly, a driving circuit of the PDP 30 is provided with an energy recovery circuit so as to reduce a power consumption of the PDP 30. The energy recovery circuit recovers a voltage charged between the address electrode lines X and re-uses it as a driving voltage upon the next discharge.
FIG. 3 shows an energy recovery circuit installed in the first address driver 36A.
Referring to FIG. 3, the energy recovery circuit 42 includes an inductor L connected, in series, between a data supplier 44 and a source capacitor Cs, first and third switches S1 and S3 connected, in parallel, between the source capacitor Cs and the inductor L, and second and fourth switches S2 and S4 connected, in parallel, between the inductor L and the data supplier 44. The data supplier 44 includes fifth and sixth switches S5 and S6 connected, in parallel, between a panel capacitor Cp and the energy recovery circuit 42.
The panel capacitor Cp is an equivalent expression of a capacitance formed between the address electrode lines X11 to X1n in the upper block 38. The second switch S2 is connected to a data voltage source Vd while the fourth and sixth switches S4 and S6 are connected to a ground voltage source GND. The source capacitor Cs recovers and charges a voltage charged in the panel capacitor Cp and re-applies the charged voltage to the panel capacitor Cp. The inductor L forms a resonant circuit along with the panel capacitor Cp. The fifth switch S5 is turned on upon application of the data pulse while being turned off upon non-application of the data pulse.
The first switch S1 is turned on when a rising-edge enable signal XE/Rup is applied from the controller 39. The second switch S2 is turned on when an external sustaining voltage Xsusup is applied from the controller 39. The second switch S2 is turned on when a falling-edge enable signal XE/Rdn is applied from the controller 39. The fourth switch S4 is turned on when an external sustaining disable signal Xsusdn is applied from the controller 39.
The energy recovery circuit included in the second address driver 36B is formed symmetrically with respect to the energy recovery circuit provided at the first address driver 36B around the panel capacitor Cp. The rising-edge enable signal XE/Rup, the external sustaining voltage Vsusup, the falling-edge enable signal XE/Rdn and the external sustaining disable signal Xsusdn are applied to the energy recovery circuit included in the upper/lower blocks 38 and 40 at the same timing.
An operation process of the energy recovery circuit included in the first and second address drivers 36A and 36B will be described with reference to FIG. 4.
First, an external sustaining voltage Xsusup is applied to the energy recovery circuit after a rising-edge enable signal XE/Rup was applied thereto. When the rising-edge enable signal XE/Rup is applied to the energy recovery circuit, a voltage charged in the source capacitor Cs is applied to the address electrode lines X11 to X1n and X21 to X2n. Then, driving signals XTop and XBottom of the address drivers 36A and 36B is raised into a sustaining level, that is, a stabilizing level prior to application of the external sustaining voltage Xsusup. The external sustaining voltage Xsusup is applied after voltage levels of the driving signals XTop and XBottom were raised into the sustaining level, to maintain the voltage levels of the driving signals XTop and XBottom at the sustaining level. At this time, a clock signal XCLK and a video data Xdata are supplied to the address drivers 36A and 36B in the upper and lower blocks 38 and 40, respectively. In other words, the video data Xdata and the clock signal XCLK as a low voltage are applied in a period at which the sustaining voltage level is stabilized so as to prevent a waveform distortion caused by a high voltage.
Subsequently, a falling-edge enable signal XE/Rdn is applied to the energy recovery circuit. When the falling-edge enable signal XE/Rdn is applied to the energy recovery circuit, the driving signals XTop and XBottom of the address drivers 36A and 36B begins a falling. At this time, the source capacitor Cs of the energy recovery circuit recovers and charges a voltage discharged from the address electrode lines X11 to X1n and X21 and X2n.
An external sustaining disable signal Xsusdn is applied to the energy recovery circuit at a half time of the falling-edge enable signal XE/Rdn. Then, the driving signals XTop and XBottom of the address drivers 36A and 36B fall into a ground voltage level. Meanwhile, the first and second scanning/sustaining drivers 32A and 32B sequentially apply negative scanning pulses YTopSCAN and YBottomSCAN synchronized with a video data pulse for each block.
However, the conventional PDP driving method has a problem in that, since the video data Xdata and the clock signal XCLK should be applied only in a period at which the driving signals XTop and XBottom of the address drivers 36A and 36B are stabilized, a scanning interval is lengthened. In other words, since a period at which the rising-edge enable signal XE/Rup and the falling-edge enable signal XE/Rdn of the energy recovery circuit are generated is added to the scanning interval besides a period at which a video data is provided, a scanning interval is lengthened to that extent.
For instance, assuming that a time required for applying video data for the upper and lower blocks 38 and 40 to each address driver 38 and 36B is 1.2 μs and a time for dividing video data for the upper and lower blocks 38 and 40 is 0.1 μs, total scanning interval becomes 2.5 μs. Since a video data having a low voltage (i.e., 5V) is transferred to the address drivers 36A and 36B in the upper and lower blocks 38 and 40 at a control circuit board (not shown) for this 2.5 μs, driving signals of the address drivers 36A and 36B having a high voltage (i.e., 70 to 80V) must be stabilized into the sustaining level. Accordingly, since a high sustaining voltage must be stabilized for 2.5 μs, a period at which the rising-edge and falling-edge enable signals of the energy recovery circuit are generated is added to the scanning interval.
Since a time occupied by an address interval within one frame becomes long as the scanning interval is lengthened as mentioned above, a time assigned for a sustaining interval is relatively reduced. As a result, the conventional driving method has a limit in a high-speed driving as well as a restriction in a high-resolution display of a picture.